Guru PRASAD
(Manipal Institute of Technology)
Kumara SHAMA
(Manipal Institute of Technology)
Yıl: 2020Cilt: 28Sayı: 1ISSN: 1300-0632 / 1300-0632Sayfa Aralığı: 500 - 508İngilizce

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A low dropout voltage regulator with a transient voltage spikes reducer and improved figure of merit
: An area efficient output capacitor-free low dropout [LDO] voltage regulator with an improved figure of meritis presented in this paper. The proposed LDO regulator consists of a novel, dynamically biased error amplifier thatreduces overshoot and undershoot voltage spikes arising from abrupt load changes. Source bulk modulation is employedto enhance the current driving capability of the pass transistor. An adaptive biasing scheme is also used along withdynamic biasing to improve the current efficiency of the system. The on-chip capacitor required for proper working ofthe LDO regulator is only 35 pF. The proposed LDO regulator is designed and simulated in 180 nm standard CMOStechnology. The LDO regulator exhibits a line regulation of 1.67 mV/V and a load regulation of 100 µV /mA. Whenload changes from 0 mA to 100 mA in 1 µs, an undershoot of 148 mV and an overshoot of 172 mV are observed. Themeasured power supply rejection ratio is 25 dB at 100 kHz. The working of the proposed LDO regulator has been testedunder all process corners and Monte-Carlo statistical analysis reveals that it is robust against process variations andlocal mismatch.
Fen > Mühendislik > Bilgisayar Bilimleri, Yapay Zeka
Fen > Mühendislik > Bilgisayar Bilimleri, Sibernitik
Fen > Mühendislik > Bilgisayar Bilimleri, Donanım ve Mimari
Fen > Mühendislik > Bilgisayar Bilimleri, Bilgi Sistemleri
Fen > Mühendislik > Bilgisayar Bilimleri, Yazılım Mühendisliği
Fen > Mühendislik > Bilgisayar Bilimleri, Teori ve Metotlar
Fen > Mühendislik > Mühendislik, Elektrik ve Elektronik
DergiAraştırma MakalesiErişime Açık
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